/*
 * Copyright (c) 2021 MediaTek Inc.
 *
 * Use of this source code is governed by a MIT-style
 * license that can be found in the LICENSE file or at
 * https://opensource.org/licenses/MIT
 */
#pragma once

#include <sys/types.h>

#define REGION(name, base, size)    name##_BASE_PHY = (uintptr_t)base, \
                                    name##_BASE     = (uintptr_t)KERNEL_ASPACE_BASE + base, \
                                    name##_SIZE     = (size_t)size

enum {
    REGION(SRAM,   0x00100000, 0x00020000),
    REGION(HWVER,  0x08000000, 0x00001000),
    REGION(MCUCFG, 0x0C000000, 0x00200000),
    REGION(GIC,    0x0C400000, 0x00400000),
    REGION(DBG,    0x0D000000, 0x00050000),
    REGION(IO,     0x10000000, 0x10000000),
    REGION(DRAM,   0x40000000, 0x40000000),
};

enum {
    TOPCLK_BASE          = IO_BASE + 0x00000000,
    INFRACFG_AO_BASE     = IO_BASE + 0x00001000,
    PERICFG_BASE         = IO_BASE + 0x00003000,
    GPIO_BASE            = IO_BASE + 0x00005000,
    APMIXED_BASE         = IO_BASE + 0x0000C000,
    PWRAP_BASE           = IO_BASE + 0x0000D000,
    INFRA_AO_BCRM_BASE   = IO_BASE + 0x00022000,
    BUS_DBG_BASE         = IO_BASE + 0x00208000,
    CCIF0_AP_BASE        = IO_BASE + 0x00209000,
    TZCC_BASE            = IO_BASE + 0x00210000,
    EMI_APB_BASE         = IO_BASE + 0x00219000,
    SUB_EMI_APB_BASE     = IO_BASE + 0x0021D000,
    DDRPHY_AO_CH0_BASE   = IO_BASE + 0x00230000,
    EMI_CHANNEL_APB_BASE = IO_BASE + 0x00235000,
    INFRA_TRACKER_BASE   = IO_BASE + 0x00314000,
    THERM_CTRL_BASE      = IO_BASE + 0x00315000,
    INFRA_BUS_HRE_BASE   = IO_BASE + 0x0032C000,
    EMI_SMPU_BASE        = IO_BASE + 0x00351000,
    EMI_SMPU2_BASE       = IO_BASE + 0x00352000,
    SUB_EMI_SMPU_BASE    = IO_BASE + 0x00355000,
    SUB_EMI_SMPU2_BASE   = IO_BASE + 0x00356000,
    DPM_PM1_SRAM_BASE    = IO_BASE + 0x00900000,
    DPM_DM1_SRAM_BASE    = IO_BASE + 0x00920000,
    DPM_CFG_CH0_BASE     = IO_BASE + 0x00940000,
    UART0_BASE           = IO_BASE + 0x01001000,
    UART1_BASE           = IO_BASE + 0x01002000,
    DISP_PWM0_BASE       = IO_BASE + 0x0100E000,
    PERI_AO_BCRM_BASE    = IO_BASE + 0x01035000,
    USB3_BASE            = IO_BASE + 0x01200000,
    USB3_IPPC_BASE       = IO_BASE + 0x01203E00,
    MSDC0_BASE           = IO_BASE + 0x01230000,
    MSDC1_BASE           = IO_BASE + 0x01240000,
    I2C10_BASE           = IO_BASE + 0x01280000,
    I2C11_BASE           = IO_BASE + 0x01281000,
    I2C12_BASE           = IO_BASE + 0x01282000,
    I2C13_BASE           = IO_BASE + 0x01283000,
    UFS0_MPHY_BASE       = IO_BASE + 0x012A0000,
    UFS0_BASE            = IO_BASE + 0x012B0000,
    UFS0_AO_CONFIG_BASE  = IO_BASE + 0x012B8000,
    I2C0_APDMA_BASE      = IO_BASE + 0x01300200,
    I2C1_APDMA_BASE      = IO_BASE + 0x01300280,
    I2C2_APDMA_BASE      = IO_BASE + 0x01300300,
    I2C3_APDMA_BASE      = IO_BASE + 0x01300480,
    I2C4_APDMA_BASE      = IO_BASE + 0x01300500,
    I2C5_APDMA_BASE      = IO_BASE + 0x01300680,
    I2C6_APDMA_BASE      = IO_BASE + 0x01300700,
    I2C7_APDMA_BASE      = IO_BASE + 0x01300780,
    I2C8_APDMA_BASE      = IO_BASE + 0x01300900,
    I2C9_APDMA_BASE      = IO_BASE + 0x01300A80,
    I2C10_APDMA_BASE     = IO_BASE + 0x01300C00,
    I2C11_APDMA_BASE     = IO_BASE + 0x01300C80,
    I2C12_APDMA_BASE     = IO_BASE + 0x01300D00,
    I2C13_APDMA_BASE     = IO_BASE + 0x01300E80,
    IOCFG_RM_BASE        = IO_BASE + 0x01C20000,
    IOCFG_RT_BASE        = IO_BASE + 0x01C30000,
    IOCFG_RMM_BASE       = IO_BASE + 0x01C40000,
    I2C1_BASE            = IO_BASE + 0x01D00000,
    I2C2_BASE            = IO_BASE + 0x01D01000,
    I2C3_BASE            = IO_BASE + 0x01D02000,
    I2C4_BASE            = IO_BASE + 0x01D03000,
    I2C7_BASE            = IO_BASE + 0x01D04000,
    I2C8_BASE            = IO_BASE + 0x01D05000,
    I2C9_BASE            = IO_BASE + 0x01D06000,
    IOCFG_BL_BASE        = IO_BASE + 0x01D10000,
    IOCFG_BM_BASE        = IO_BASE + 0x01D30000,
    IOCFG_BR_BASE        = IO_BASE + 0x01D40000,
    IOCFG_BRR_BASE       = IO_BASE + 0x01D50000,
    IOCFG_LB_BASE        = IO_BASE + 0x01D60000,
    I2C0_BASE            = IO_BASE + 0x01E00000,
    I2C5_BASE            = IO_BASE + 0x01E01000,
    I2C6_BASE            = IO_BASE + 0x01E02000,
    IOCFG_LM_BASE        = IO_BASE + 0x01E10000,
    USB3_SIF2_BASE       = IO_BASE + 0x01E40000,
    MIPI_TX0_CONFIG_BASE = IO_BASE + 0x01E50000,
    MIPI_TX1_CONFIG_BASE = IO_BASE + 0x01E60000,
    MSDC1_TOP_BASE       = IO_BASE + 0x01E70000,
    EFUSE_BASE           = IO_BASE + 0x01EE0000,
    IOCFG_RTT_BASE       = IO_BASE + 0x01EA0000,
    IOCFG_TR_BASE        = IO_BASE + 0x01F10000,
    IOCFG_TL_BASE        = IO_BASE + 0x01F20000,
    IOCFG_LT_BASE        = IO_BASE + 0x01F30000,
    MSDC0_TOP_BASE       = IO_BASE + 0x01F50000,
    MMSYS_CONFIG_BASE    = IO_BASE + 0x04000000,
    MM_MUTEX_BASE        = IO_BASE + 0x04001000,
    OVL0_BASE            = IO_BASE + 0x04002000,
    DISP_OVL1_2L_BASE    = IO_BASE + 0x04003000,
    DISP_OVL0_2L_BASE    = IO_BASE + 0x04004000,
    DISP_RDMA0_BASE      = IO_BASE + 0x04006000,
    DISP_TDSHP0_BASE     = IO_BASE + 0x04007000,
    DISP_C3D0_BASE       = IO_BASE + 0x04008000,
    DISP_COLOR0_BASE     = IO_BASE + 0x04009000,
    DISP_CCORR0_BASE     = IO_BASE + 0x0400A000,
    DISP_CCORR1_BASE     = IO_BASE + 0x0400B000,
    DISP_MDP_AAL0_BASE   = IO_BASE + 0x0400C000,
    DISP_AAL0_BASE       = IO_BASE + 0x0400D000,
    DISP_GAMMA0_BASE     = IO_BASE + 0x0400E000,
    DISP_POSTMASK0_BASE  = IO_BASE + 0x0400F000,
    DISP_DITHER0_BASE    = IO_BASE + 0x04010000,
    DISP_CHIST0_BASE     = IO_BASE + 0x04011000,
    DISP1_CHIST0_BASE    = IO_BASE + 0x04012000,
    DISP_CM0_BASE        = IO_BASE + 0x04013000,
    DISP_SPR0_BASE       = IO_BASE + 0x04014000,
    DISP_DSC_BASE        = IO_BASE + 0x04015000,
    DISP_DSI0_BASE       = IO_BASE + 0x04017000,
    SMI_LARB0_BASE       = IO_BASE + 0x04021000,
    SMI_LARB1_BASE       = IO_BASE + 0x04022000,
    MMSYS1_CONFIG_BASE   = IO_BASE + 0x04400000,
    MM1_MUTEX_BASE       = IO_BASE + 0x04401000,
    DISP1_OVL0_BASE      = IO_BASE + 0x04402000,
    DISP1_OVL1_2L_BASE   = IO_BASE + 0x04403000,
    DISP1_OVL0_2L_BASE   = IO_BASE + 0x04404000,
    DISP1_RDMA0_BASE     = IO_BASE + 0x04406000,
    DISP_RDMA1_BASE      = IO_BASE + 0x04406000,
    DISP_TDSHP1_BASE     = IO_BASE + 0x04407000,
    DISP_C3D1_BASE       = IO_BASE + 0x04408000,
    DISP_COLOR1_BASE     = IO_BASE + 0x04409000,
    DISP_CCORR0_1_BASE   = IO_BASE + 0x0440A000,
    DISP_CCORR1_1_BASE   = IO_BASE + 0x0440B000,
    DISP_MDP_AAL1_BASE   = IO_BASE + 0x0440C000,
    DISP_AAL1_BASE       = IO_BASE + 0x0440D000,
    DISP_GAMMA1_BASE     = IO_BASE + 0x0440E000,
    DISP_POSTMASK1_BASE  = IO_BASE + 0x0440F000,
    DISP_DITHER1_BASE    = IO_BASE + 0x04410000,
    DISP_CHIST1_BASE     = IO_BASE + 0x04411000,
    DISP1_CHIST1_BASE    = IO_BASE + 0x04412000,
    DISP_CM1_BASE        = IO_BASE + 0x04413000,
    DISP_SPR1_BASE       = IO_BASE + 0x04414000,
    DISP_DSI1_BASE       = IO_BASE + 0x04417000,
    APUSYS_BASE          = IO_BASE + 0x09000000,
    VLP_BASE             = IO_BASE + 0x0C000000,
    VLPCFG_BASE          = IO_BASE + 0x0C00C000,
    SPM_BASE             = IO_BASE + 0x0C001000,
    SPM_SRAM_BASE        = IO_BASE + 0x0C002000,
    RGU_BASE             = IO_BASE + 0x0C007000,
    SEJ_BASE             = IO_BASE + 0x0C009000,
    SECURITY_AO_BASE     = IO_BASE + 0x0C00B000,
    SRCLKEN_RC_BASE      = IO_BASE + 0x0C00D000,
    KPD_BASE             = IO_BASE + 0x0C00E000,
    DVFSRC_BASE          = IO_BASE + 0x0C00F000,
    VLP_AO_BCRM_BASE     = IO_BASE + 0x0C017000,
    SCP_ADDR_BASE        = IO_BASE + 0x0C400000,
    PMIF_SPMI_BASE       = IO_BASE + 0x0C015000,
    SPMI_MST_BASE        = IO_BASE + 0x0C801000,
    AOC_BASE             = IO_BASE + 0x0C803000,
    ADSP_BASE            = IO_BASE + 0x0E000000,
    SMI_SUBCOM0_BASE     = IO_BASE + 0x0E809000,
    SMI_SUBCOM1_BASE     = IO_BASE + 0x0E80A000,
    SMI_SUBCOM4_BASE     = IO_BASE + 0x0E817000,
    SMI_SUBCOM5_BASE     = IO_BASE + 0x0E818000,
    SMI_SUBCOM3_SYS_BASE = IO_BASE + 0x0E80D000,
    SMI_SUBCOM4_SYS_BASE = IO_BASE + 0x0E80E000,
    MMINFRA_BUS_HRE_BASE = IO_BASE + 0x0E900000,
    VCP_ADDR_BASE        = IO_BASE + 0x0EA00000,
};
